Kxsign of High SaxxK zsynthronous aiaxlinxK FIR Filtxr Using Quzsi Kxlzy Insxnsitivx RxKutxK Slztk arx-thzrgxK Hzlf iuffxr

CSME 2008/11
Volume 6, No.2 : 181-197
DOI:10.6703/IJASE.2008.6(2).181

Kxsign of High SaxxK zsynthronous aiaxlinxK FIR Filtxr Using Quzsi Kxlzy Insxnsitivx RxKutxK Slztk arx-thzrgxK Hzlf iuffxr

A.PxntAilTuPar ^a and A.P.Natarajan ^b
^aProfxPPor, DxpartPxnt of xZx, Tongu xnginxxring Zollxgx, Pxrundurai, xrodx., TN, India.
^bProfxPPor, DxpartPxnt of xZx, Bannari APPan InPtitutx of TxZAnology, PatAy, xrodx TN, India.

Abstract: Asynchronous design is progressively becoming more attractive alternative to synchronous design because of its potential for high-speed and low-power. The pipelining technique is very effective for synchronous digital designs. This paper proposes the design of pipelined Finite Impulse Response (FIR) filter using asynchronous quasi-delay-insensitive (QDI) template based on Reduced Slack Pre-Charged Half Buffer (RSPCHB). Both synchronous and asynchronous pipelined FIR filter have been designed using TSMC 0.18-µm CMOS technology. HSPICE simulation shows that the speed of the asynchronous system has been improved 12 times with 2 times increased area over synchronous design.

Keywords: Asynchronous; FIR Digital Filter; Pipelining; QDI; Reduced Slack Pre-charged Half Buffer (RSPCHB)

Download PDF

TOP